The present invention relates generally to semiconductor packaging and manufacturing, and more particularly to a package for a semiconductor die.
Recently, electronic systems have incorporated high-level semiconductor devices, such as integrated circuits, to perform complex processing functions. The integrated circuits include diodes, resistors, capacitors, transistors, and microprocessors. These devices are commonly connected together on the integrated circuit or semiconductor die. The semiconductor die is packaged in a structure which includes terminal connections which may be connected to a printed circuit board or other substrate. The resulting semiconductor die may be connected to multiple integrated circuits to perform multiple functions in the electronic system.
The demand in integrated circuit design has increased toward smaller circuits via miniaturization which can perform more functions. One technique is to increase the functions and decrease the size of the circuit. Another technique is to increase the circuit density of the semiconductor die. To achieve these demands, more input/output connections are formed from the semiconductor die to a surface of the substrate.
Generally, the semiconductor die is initially mounted to a die receiving area. The die protrudes from a surface of the substrate, and is electrically connected to the substrate by the bond wires. Known methods for forming the electrical connections include wirebonding and tape-automated bonding (TAB). In TAB, metal tape leads are attached between bond pads on the semiconductor die and bond pads on the substrate. An encapsulant may be used to cover the bond wires and metal tape leads to prevent contamination. In wirebonding, a plurality of bond wires are attached one at a time from each bond pad on the semiconductor die to a corresponding bond pad on the substrate. After the electrical connections ate formed and the die is encapsulated, a trim and form operation is used to separate the die from the package into individual integrated circuits.
Several types of packaging are known. Typical packages include ball grid array (BGA), flip chip, microBGA, fine pitch BGA, and chip scale packages.
Currently, each of these packages requires special tooling and supplies to form the package. One drawback to the current package designs is that they do not provide adequate structural support for the non-active surface (i.e. the surface of the die which is not connected to the die receiving area) of the semiconductor die during the packaging process. This causes chip failure because the chip tends to crack or fracture. This means that the portion of the tape between adjacent dice tends to crack during the trim and form process. This is because the tape is not adequately supported between adjacent dice on the substrate. Another drawback is that the current substrates do not provide a suitable recessed surface for the TAB applications.
Therefore, a need exists for a semiconductor package that protects the die from cracking or fracturing during a semiconductor packaging process.
In general, the invention is directed to a semiconductor package which includes a substrate having a die-mounting area. The die-mounting area forms a cavity to receive a semiconductor die such that an active surface of the die is planar with the top surface of the substrate.
Accordingly, the invention provides a method for fabricating semiconductor packages. The method includes forming a leadframe with a plurality of downset portions, attaching semiconductor dies to the downset portions, each semiconductor die including contact pads, attaching a tape to the leadframe and the dies, the tape including electrical traces, and electrically connecting the contact pads of the dies with the electrical traces of the tape.
The invention also provides a method for fabricating a semiconductor package that includes the steps of forming a substrate having a downset portion, attaching a semiconductor die to the downset portion, the semiconductor die including contact pads, attaching a tape to the substrate and the die, the tape including electrical traces, and electrically connecting the contact pad of the die with the electrical traces of the tape.
In one aspect, the semiconductor package a substrate having a first surface, a downset portion extending from the substrate to form a cavity, a semiconductor die having contact areas and being attached to the downset portion within the cavity, and a tape including circuit traces attached to the first surface, the circuit traces of the tape being electrically connected to the contact areas of the semiconductor die.
Implementations of the invention include one or more of the following. The substrate may be formed from ceramic, plastic, or metal alloy. The substrate may include a plurality of first bond pads formed on the first surface, and a plurality of conductive terminals formed on the first surface. A plurality of circuit traces may be formed on the first surface to form an electrical path between selected ones of the first bond pads and the conductive terminals. The semiconductor die may include a plurality of second bond pads formed on the active surface of the die, and the semiconductor package may include a plurality of electrical connections formed between selected ones of the first and second bond pads. The electrical connections may be formed by wirebonding. The plurality of conductive terminals may be in electrical communication with a plurality of corresponding terminals on a printed circuit board. The circuit traces may be formed from aluminum, gold, or copper. An encapsulating layer may be formed on the package to encapsulate the electrical connections. The conductive terminals may be formed from gold or copper, and the first bond pads may be formed from gold or copper. A layer of tape having circuitry may be employed to apply circuitry to the active surface of the semiconductor die. The substrate may include a plurality of second indexing holes, and the tape of material may include a plurality of first indexing holes such that the first indexing holes and the second indexing holes are aligned when the circuitry is formed on the active surface of the semiconductor die. The die paddle may include a surface operable to dissipate heat. The tape of circuitry may be formed from metal. The tape of circuitry may be co-planar with the first surface.
In another aspect, the invention is directed to an electronic circuit having a substrate which includes a first surface and a second surface. The frame is formed on the first surface to define an opening in the substrate. A plurality of bars extend from the second surface of the substrate, and a die paddle extends between the plurality of bars to form a cavity to receive at least one semiconductor die. An active surface of the semiconductor die is planar with the first surface of the substrate. A printed circuit board is positioned relative to the substrate, and a plurality of electrical connections are formed between the active surface of the semiconductor die and the printed circuit board. The package may include first and second rails formed integral with or mounted on the first surface of the substrate.
In another aspect, the invention is directed to a semiconductor package which includes a substrate having a first surface and a second surface. A plurality of die-mounting areas are formed in the substrate for receiving a plurality of semiconductor dice. Each of the die-mounting areas include a frame formed on the first surface of the substrate to define an opening in the substrate, and a plurality of bars extending from the second surface of the substrate. A die paddle is formed between the plurality of bars to form a cavity to receive one of the semiconductor dice such that an active surface of the semiconductor die is planar with the first surface of the substrate.
These and other advantages and features of the invention will be more readily understood from the following detailed description of the invention that is provided in connection with the accompanying drawings.